A New Physical Modeling of Parasitic Capacitances of Deep-Submicron LDD MOSFETs

In mixed circuit simulation, the estimation of parasitic capacitances of deep-submicron MOSFETs is very important. With the continuous scaling of the devices, the extrinsic capacitance, i.e. the overlap and fringing capacitances become a growing fraction of the total gate capacitance. We found the major existing models do not predict correctly the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper, we present a new approach to model these two capacitances in currentless regime. The bias dependence of each components of the extrinsic capacitance is investigated and a study of the influence of the LDD doping dose is also led. Then, an efficient, simple and continuous model describing the evolution of the extrinsic capacitance in all operating regimes of a nchannel LDD MOSFET is developed. This model is finally incorporated in a existing compact-model for circuit simulation. We show the new model leads to excellent results in comparison with full 2D numerical device simulations.